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<title>XADD—Exchange and Add </title></head>
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<h1>XADD—Exchange and Add</h1>
<table>
<tr>
<th>Opcode</th>
<th>Instruction</th>
<th>Op/En</th>
<th>64-Bit Mode</th>
<th>Compat/Leg Mode</th>
<th>Description</th></tr>
<tr>
<td>0F C0 /<em>r</em></td>
<td>XADD <em>r/m8, r8</em></td>
<td>MR</td>
<td>Valid</td>
<td>Valid</td>
<td>Exchange <em>r8</em> and <em>r/m8</em>; load sum into <em>r/m8</em>.</td></tr>
<tr>
<td>REX + 0F C0 /<em>r</em></td>
<td>XADD <em>r/m8*, r8*</em></td>
<td>MR</td>
<td>Valid</td>
<td>N.E.</td>
<td>Exchange <em>r8</em> and <em>r/m8</em>; load sum into <em>r/m8</em>.</td></tr>
<tr>
<td>0F C1 /<em>r</em></td>
<td>XADD <em>r/m16, r16</em></td>
<td>MR</td>
<td>Valid</td>
<td>Valid</td>
<td>Exchange <em>r16</em> and <em>r/m16</em>; load sum into <em>r/m16</em>.</td></tr>
<tr>
<td>0F C1 /<em>r</em></td>
<td>XADD <em>r/m32, r32</em></td>
<td>MR</td>
<td>Valid</td>
<td>Valid</td>
<td>Exchange <em>r32</em> and <em>r/m32</em>; load sum into <em>r/m32</em>.</td></tr>
<tr>
<td>REX.W + 0F C1 /<em>r</em></td>
<td>XADD <em>r/m64, r64</em></td>
<td>MR</td>
<td>Valid</td>
<td>N.E.</td>
<td>Exchange <em>r64</em> and <em>r/m64</em>; load sum into <em>r/m64</em>.</td></tr></table>
<p><strong>NOTES:</strong></p>
<p>*</p>
<p>In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.</p>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>MR</td>
<td>ModRM:r/m (r, w)</td>
<td>ModRM:reg (r, w)</td>
<td>NA</td>
<td>NA</td></tr></table>
<h2>Description</h2>
<p>Exchanges the first operand (destination operand) with the second operand (source operand), then loads the sum of the two values into the destination operand. The destination operand can be a register or a memory location; the source operand is a register.</p>
<p>In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits.</p>
<p>This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.</p>
<h2>IA-32 Architecture Compatibility</h2>
<p>IA-32 processors earlier than the Intel486 processor do not recognize this instruction. If this instruction is used, you should provide an equivalent code sequence that runs on earlier processors.</p>
<h2>Operation</h2>
<pre>TEMP ← SRC + DEST;
SRC ← DEST;
DEST ← TEMP;</pre>
<h2>Flags Affected</h2>
<p>The CF, PF, AF, SF, ZF, and OF flags are set according to the result of the addition, which is stored in the destination operand.</p>
<h2>Protected Mode Exceptions</h2>
<table class="exception-table">
<tr>
<td>#GP(0)</td>
<td>
<p>If the destination is located in a non-writable segment.</p>
<p>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</p>
<p>If the DS, ES, FS, or GS register contains a NULL segment selector.</p></td></tr>
<tr>
<td>#SS(0)</td>
<td>If a memory operand effective address is outside the SS segment limit.</td></tr>
<tr>
<td>#PF(fault-code)</td>
<td>If a page fault occurs.</td></tr>
<tr>
<td>#AC(0)</td>
<td>If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.</td></tr>
<tr>
<td>#UD</td>
<td>If the LOCK prefix is used but the destination is not a memory operand.</td></tr></table>
<h2>Real-Address Mode Exceptions</h2>
<table class="exception-table">
<tr>
<td>#GP</td>
<td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr>
<td>#SS</td>
<td>If a memory operand effective address is outside the SS segment limit.</td></tr>
<tr>
<td>#UD</td>
<td>If the LOCK prefix is used but the destination is not a memory operand.</td></tr></table>
<h2>Virtual-8086 Mode Exceptions</h2>
<table class="exception-table">
<tr>
<td>#GP(0)</td>
<td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr>
<td>#SS(0)</td>
<td>If a memory operand effective address is outside the SS segment limit.</td></tr>
<tr>
<td>#PF(fault-code)</td>
<td>If a page fault occurs.</td></tr>
<tr>
<td>#AC(0)</td>
<td>If alignment checking is enabled and an unaligned memory reference is made.</td></tr>
<tr>
<td>#UD</td>
<td>If the LOCK prefix is used but the destination is not a memory operand.</td></tr></table>
<h2>Compatibility Mode Exceptions</h2>
<p>Same exceptions as in protected mode.</p>
<h2>64-Bit Mode Exceptions</h2>
<table class="exception-table">
<tr>
<td>#SS(0)</td>
<td>If a memory address referencing the SS segment is in a non-canonical form.</td></tr>
<tr>
<td>#GP(0)</td>
<td>If the memory address is in a non-canonical form.</td></tr>
<tr>
<td>#PF(fault-code)</td>
<td>If a page fault occurs.</td></tr>
<tr>
<td>#AC(0)</td>
<td>If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.</td></tr>
<tr>
<td>#UD</td>
<td>If the LOCK prefix is used but the destination is not a memory operand.</td></tr></table></body></html>